The present invention relates to a random logic circuit and, more particularly, to a random logic circuit capable of preventing a sub-threshold leak current in sleep mode.
In recent LSI, it has been intended to reduce operating power source voltage, and to operate the LSI, a technology has been used for lowering threshold voltage of a transistor forming an internal circuit of the LSI.
However, as the sub-threshold leak current is increased in proportion to the lowering of the threshold voltage of the transistor, it is an important problem how to prevent the increase of the sub-threshold leak current.
In semiconductor memory, to reduce the sub-threshold leak current in the internal circuit at the time of standby cycle, a technology called hierarchical power source system has been developed.
FIG. 10 is a diagram showing a hierarchical system. In an internal circuit comprising inverters (X1, X2, X3) connected in series forming a plurality of stages, each inverter comprises a CMOS. As shown in FIG. 10, sources of a PMOS transistor and a NMOS transistor are respectively connected to main power source line L1, sub power source line L2, main grounding line L3 and sub-grounding line L4 corresponding to the condition at the time of stand-by cycle. In this system, at the time of stand-by cycle, a negative potential is applied to a gate, whereby the sub-threshold leak current generated in the internal circuit is reduced.
In MTCMOS circuit, to reduce the sub-threshold leak current in sleep mode, there is a system in which power source of the internal circuit is switched off. In this system, a latch circuit called balloon circuit is connected to the internal circuit, and data inputted to the internal circuit are also inputted to the balloon circuit. In sleep mode, when the power source of the internal circuit is off, the internal circuit and the balloon circuit are disconnected from each other, and the data inputted to the internal circuit disappear. However, as the same data are stored in the balloon circuit, the data can be transferred from the balloon circuit to the internal circuit when the power source is on.
A random logic circuit is hereinafter described.
FIG. 11 is a diagram showing an arrangement of a conventional random logic. Symbol F/F indicates a flip-flop circuit for receiving data from a logic circuit of former stage, holding the data, and outputting the data to a logic circuit of latter stage. In the drawing, reference numerals 200 to 205 indicate buffer circuits, numerals 206 to 211 indicate flip-flop circuits, and numerals 212 to 214 indicate logic circuits. Numerals 215 to 220 indicate flip-flop circuits, numerals 221 to 223 indicate logic circuits, and numerals 224 to 229 indicate flip-flop circuits. Numerals 230 to 232 indicate logic circuits, and numerals 233 to 238 indicate flip-flop circuits. An input signals inputted to the buffer circuits 200 to 205 are respectively inputted to the flip-flop circuits 206 to 211 and held there. The held data are then outputted to the logic circuits 212 to 214 corresponding to the content processed. Results obtained after the processing in the logic circuits 212 to 214 are outputted to the flip-flop circuits 215 to 220 and held there. In this manner, the data processing is performed in order by a logic circuit and a flip-flop circuit connected to the latter stage.
FIG. 12 is a diagram showing an arrangement of the flip-flop circuit shown in FIG. 11. The flip-flop circuit is controlled using complementary two-phase clocks (CKB signal and CK signal) by a control circuit not shown, thus holding and shifting operations of data are performed.
The data from the logic circuit or the buffer circuit of former stage are inputted to an input terminal D and further inputted to a latch portion of former stage through an inverter 239 during activation period of CKB signal (CK signal is inactive). The latch portion of former stage comprises an inverter 240 and an inverter 241.
Then, the data are held in the latch portion of former stage during activation period of CK signal (CKB signal is inactive), transferred to a latch portion of latter stage through an transfer gate 242, and outputted from an output terminal Q through inverters 243 and 245. The latch portion of latter stage comprises the inverter 243 and an inverter 244. During activation period of next CKB signal (while CK signal being inactivated), the data outputted from the transfer gate 242 are held in the latch portion of latter stage.
As described above, as far as semiconductor memory or MTCMOS circuit is concerned, there is a method for preventing sub-threshold leak current occurring at the time of stand-by cycle or in sleep mode. However, a problem exists in that such a method of prevention is not applicable to the random logic memory.
More specifically, in sleep mode, as data held in the flip-flop circuit are varied depending on the content processed in the logic circuit of former stage, the data are not always uniform being different from those held in the semiconductor memory. Even if adopting any hierarchical system in the random logic circuit, there is a problem that generation of the sub-threshold leak current cannot be prevented depending on the content of input data.
There is another problem that in case of providing any balloon circuit, it is necessary to establish a path of data in addition to signal path for normal access, which results in rather complicated control of the internal circuit of the random logic circuit.
Accordingly, the present invention was made to solve the above-discussed problems and has an object of providing a random logic circuit capable of preventing a sub-threshold leak current.
This object and advantages are achieved by providing a new and improved random logic circuit including: an input portion for inputting data; a first latch portion for receiving the data outputted from the input portion, and holding and outputting the data; a second latch portion for receiving the data outputted from the first latch portion, and holding and outputting the data; an output portion for receiving the data outputted from the second latch portion and outputting the data to a logic circuit; and a prevention circuit for preventing generation of a sub-threshold leak current in sleep mode between the first latch portion and the second latch portion.
The above object and novel features of the invention will more fully appear from the following derailed description when the same is read in connection with the accompanying drawing. It is to be expressly understood, however, that the drawing is for purpose of illustration only and is not intended as a definition of the limits of the invention.